1. Field
This application relates generally to circuit fabrication, and more specifically to mask alignment in a lithography process.
2. Related Art
The fabrication of semiconductors is a process requiring precision. Since the size of the structures defined by the masks in a lithography process are on the order of a micron or less, it is vital that the masks are aligned properly with very little deviation. As circuit components continue to shrink, mask alignment offset tolerance becomes ever smaller, causing mask alignment to become an increasingly difficult task.
In one exemplary embodiment, a lithography process includes forming a first grating having lines and spaces on a wafer using a first mask having a pattern for the first grating. A second grating is formed having lines and spaces on the wafer using a second mask having a pattern for the second grating and also the pattern for forming the first grating. Any misalignment between the first and second masks can be determined based on the difference in either the width of the lines or width of the spaces of the first and second gratings formed on the wafer.
The present invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawings and claims.